The second Intel Edge Technology Training event brought together Intel engineers and Intel partners from across Europe for two days of presentations on various edge technology topics. These were divided into subtopics of real-time computing, AI, security, and safety. I had the opportunity to present under the real-time computing category, where my talk, “Achieving Determinism on x86 with the RTS Hypervisor and Intel TCC”, provided an accessible look into Time-Coordinated Computing (TCC) and how the RTS Hypervisor can simplify it.
Here’s a summary of the session.
The Challenge of Real-Time Computing on x86
When we founded Real-Time Systems nearly 20 years ago, many doubted the feasibility of achieving "hard real-time" on x86 architecture. The primary concern often revolved around the cache. While we could discuss the specifics of real-time requirements and different processor architectures, the cache was often mentioned as a significant obstacle.
We were determined to create a real-time hypervisor that could run on any PC. In the early days, I experimented with running an operating system without using the cache to see if it would improve stability. Unsurprisingly, performance was very slow, but the surprising part was that memory access times varied greatly, making it impractical.
Importance of Caches and Mitigating Interference with CAT
Caches are crucial for both stability and performance. With the RTS Hypervisor, real-time tasks run alongside standard software on separate CPU cores. Shared caches can be problematic because if a real-time task needs quick access to data, but the cache is filled with unrelated information, it slows things down. Intel’s Cache Allocation Technology (CAT) addresses this issue by dividing the cache into sections that separate operating systems can use separately.
Initially, not all our tests with CAT showed immediate improvement. However, after developing specific tests to measure memory access times under stress, we saw significant benefits. CAT proved to be very effective, though it’s not the only solution for ensuring tasks run on time without interference. That’s why we've added more features to meet our customers' needs.
Hypervisor Design, Low-Level Control, and TCC Integration
Ensuring tasks run on time without interference is critical. The RTS Hypervisor is designed to focus on real-time tasks and protect them from general-purpose tasks that can disrupt timing.
As a Type I hypervisor, the RTS Hypervisor starts right after the firmware, allowing important settings to be applied before other operating systems start. It doesn’t rely on any operating system kernel, ensuring full control with minimal resource use, which is important for security and real-time performance.
Basic timing accuracy on a PC requires control over power management, ACPI settings, and preventing System Management Interrupts (SMI). Various CPU and PCI-specific settings, especially Model-Specific Registers (MSR), are also important. While Intel’s processors support backward compatibility, achieving the best timing accuracy requires model-specific support.
The RTS Hypervisor integrates Intel’s TCC and real-time support, so operating systems and applications can benefit automatically without needing changes. Despite concerns about virtualization overhead, our approach allows real-time tasks to run more deterministically on the RTS Hypervisor compared to running directly on the PC. This is because many operating systems don’t fully control the system, leaving it to firmware or Board Support Packages (BSP), which focus more on device support than timing accuracy.
Protecting real-time tasks from general-purpose tasks, like those on Windows or Ubuntu, is essential because these systems are designed for general use, not strict timing. The RTS Hypervisor uses Intel’s TCC features to keep real-time tasks running smoothly despite other tasks running in parallel.
Automatic and Adjustable System Configuration
Most TCC functions work automatically without needing configuration. The RTS Hypervisor has different modes for real-time and general-purpose operating systems, applying necessary settings and prioritizing real-time tasks. Settings like fixed frequencies and divided caches are usually automatic but can be adjusted easily.
For example, shared caches can be automatically assigned based on the operating systems in use. Frequencies can be set system-wide or per operating system, with dynamic frequencies allowed for general-purpose tasks. Extreme values are adjusted automatically to fit the system’s capabilities, ensuring optimal performance.
CPU core assignments are flexible, allowing configurations based on number, percentage, or type of cores (P-cores, E-cores, LP E-cores). This flexibility ensures compatibility across different systems, even with varying CPU and cache setups.
Conclusion
To summarize, our RTS Hypervisor includes essential timing accuracy and isolation features, such as power management, ACPI, SMI, and CAT. We provide default settings with options for adjustments, ensuring reliable real-time performance and protection from interference.
The flexibility in configuring shared caches, CPU frequencies, and core assignments makes the RTS Hypervisor adaptable across different systems, even with varying CPU and cache setups. This ensures that real-time tasks can run smoothly alongside general-purpose tasks without compromising on performance or stability.
As we continue to innovate and improve our solutions, our commitment remains focused on delivering the highest levels of determinism and temporal isolation for real-time computing on x86 architecture. We are excited about the future and the possibilities that Intel TCC and our RTS Hypervisor bring to the realm of real-time systems.
Thank you for reading. If you have any questions or would like to learn more about our products and how they can benefit your applications, feel free to reach out.
